This invention relates in general to analog-to-digital (A/D) converters, and more particularly, to an A/D converter including a multi-stage cascaded sigma delta (.SIGMA..DELTA.) modulator wherein a digital correction technique is utilized for compensation of gain mismatches between the stages thereof.
Analog-to-digital converters are well enough known in the art and many techniques have been developed for achieving the conversion from analog to digital format. One A/D converter known of U.S. Pat. No. 4,704,600 issued to Uchimura et al includes a triple-cascade .SIGMA..DELTA. modulator wherein a continuous time analog input signal is sampled and quantized into three 1-bit digital output signals. As brought out in the '600 patent, the first and second stages also generate error signals of the difference between the actual magnitude of the input signals and the quantized output signals. In the triple-cascade approach, the error signal of the first stage is applied into the input of the second stage, and the error signal of the second stage is applied to the input of the third stage. These error signals are known as quantization error and can cause distortion in the digital output signal of the A/D converter. The quantized output signals of the three stages are recombined with the associated word growth and low-pass filtered to provide a multi-bit digital output signal representative of the magnitude of the analog input signal.
The aforementioned low-pass filtering is provided via a comb filter, the latter of which is thoroughly described in U.S. Pat. No. 4,876,542 issued to van Bavel et al and assigned to Motorola, Inc. The comb filter includes a number of serially coupled digital integrators and an equal number of serially coupled digital differentiators wherein the number determines the order of the filter. For a third order comb filter the output of the first stage of the .SIGMA..DELTA. modulator is coupled to the first integrator, while the outputs of the second and third stages are coupled to the second and third integrators, respectively. The digital integrators operate at the oversampling frequency F.sub.S, while the digital differentiators operate at a predetermined lower frequency. The ratio of the oversampling frequency F.sub.S to the predetermined lower frequency is known as the decimation ratio. The multi-bit digital output signal is provided at the output of the last digital differentiator in the chain.
The theoretic performance of the A/D converter is determined by the oversampling frequency F.sub.S of the input signal which is typically 64 times the Nyquist sampling frequency. The Fourier transform of the .SIGMA..DELTA. quantization error signal provides a spectrum of energy in the frequency domain from zero to one-half the oversampling frequency F.sub.S. The triple-cascade .SIGMA..DELTA. modulator tends to shape the distribution of the energy as an exponential-like function of frequency having the majority of the energy in the upper band of the spectrum allowing the lower frequency utilization band (in-band range) to be low-pass filtered thereby removing much of the quantization error and reducing the .SIGMA..DELTA. modulator quantum. This quantum is defined as the differential magnitude within which the input signal is resolved, and it is a function of the number of bits of resolution and the full-scale range of the input signal, thus, for one bit of resolution the quantum is the full-scale range of the input signal. By reducing the quantization energy within the in-band range, the resolution of the multi-bit digital output signal may be increased since the discrepancy between the actual magnitude of the analog input signal at a particular sample point and the assigned quantized value is reduced, that is, the magnitude of the quantum becomes smaller.
A major contributor to the quantization error is the mismatches between the gain factors associated with the .SIGMA..DELTA. modulator stages. For ideal operation, the gain factors of the first, second and third stages must precisely match to achieve total cancellation of common error terms during the recombination of the quantized output signals thereof. However, the .SIGMA..DELTA. modulator stages typically include switched capacitor integrators for averaging the input signal, and it is beyond the capability of most if not all manufacturing processes to hold the tolerance on the capacitors within the boundaries necessary to achieve identical transfer functions for each stage. If the gains of the first, second and third stages do not exactly match, then total cancellation of common error terms generated in the .SIGMA..DELTA. modulator does not occur allowing leakage of the first order error signals and reducing the accuracy and resolution the multi-bit digital output signal. The error signal of the first stage is the most troublesome since it is comparing the full-scale range of the analog input signal to a 1-bit resolution output signal thus creating an undesirably large quantum. Hence, one problem with the aforementioned prior art is its sensitivity to the individual gains of the triple-cascaded stages. Rather than attempt to hold difficult tolerances on the manufacturing process, it would be more desirable to simply compensate for gain mismatches with a correction factor during normal operation. Compensation techniques for gain matching are discussed in the prior art; however, the teachings center around the .SIGMA..DELTA. modulator and as such are typically analog in nature and limited in providing highly accurate compensation due to frequency dependent transfer function of the analog gain correction circuitry.
Hence, what is needed is an improved A/D converter comprising a multi-stage cascaded .SIGMA..DELTA. modulator, the output of which is coupled through a comb filter for providing the digital output signal wherein a digital correction technique is utilized within the comb filter to compensate for gain mismatches between the .SIGMA..DELTA. modulator stages thereby increasing the resolution of the digital output signal. The digital correction factor may be determined through a calibration cycle during test, or even as part of a power-up initialization sequence.